1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a layout in a semiconductor chip.
2. Description of the Background Art
Recently, from a viewpoint of cost reduction, reduction in a chip area has been demanded in a semiconductor integrated circuit such as a microcomputer. In addition, higher operation speed and lower power consumption have also been demanded in a semiconductor integrated circuit.
For example, Japanese Patent Laying-Open No. 08-125130 discloses a semiconductor integrated circuit aiming to stabilize a circuit operation by reducing crosstalk or noise due to capacitive coupling between signal lines located in different interconnection layers in a semiconductor integrated circuit having a multilayer interconnection. Having a plurality of metal interconnection layers, the semiconductor integrated circuit includes a signal line as well as a ground line and a power supply line arranged in parallel to each other on respective opposing sides of the signal line in an identical interconnection layer and fixed to a ground potential and a power supply voltage potential respectively. The semiconductor integrated circuit is characterized in that the signal line, the ground line and the power supply line are arranged proximate to each other to such an extent that a spacing therebetween is set to at most a thickness of an interlayer insulating layer electrically insulating interconnections located in different interconnection layers.
In the conventional semiconductor integrated circuit, a pad and an I/O buffer (or a protection circuit such as an off-transistor and a diode) are arranged proximate to each other in a periphery of a chip. When the pad and the I/O buffer (or the protection circuit) are arranged in such a manner, reduction in a chip size is restricted.
For example, if a semiconductor integrated circuit implements a microcomputer, circuits such as a CPU (Central Processing Unit), an ROM (Read Only Memory), an RAM (Random Access Memory), and the like are mounted on a chip. Here, each circuit is constituted of elements such as an MOS (Metal Oxide Semiconductor) transistor or a capacitor. As these elements are reduced in size through microfabrication, scale of each circuit can be made smaller.
On the other hand, the size of the pad or the I/O buffer (or the protection circuit) cannot be made smaller, along with size reduction of the circuit such as a CPU. As the I/O buffer or the protection circuit protects an internal circuit (such as a CPU, an ROM, an RAM, and the like) against noise or surge introduced from the outside, sufficient area thereof is required. In the conventional semiconductor integrated circuit, the I/O buffer or the protection circuit is arranged in proximity to the pad. Therefore; if a protection circuit having a large area is provided in a region between pads or a region between the pad and the CPU, length of four sides of the chip is determined by the pad and the protection circuit, which prevents reduction in chip size.
Meanwhile, if the area of the pad or a spacing between the pads is significantly made smaller, defects in manufacturing may increase in an assembly step such as dicing or wire bonding. Therefore, an area of the pad or a pitch between the pads cannot significantly be changed in an attempt to reduce the chip size.
In preparing a broader product range in order to meet various demands from customers, generally, product variety is reinforced by varying a capacity of the RAM or the ROM, without substantially modifying the CPU. Even if the CPU, the RAM and the ROM are arranged so as not to leave an empty space in the semiconductor chip in a certain product, however, there is an empty space created in the chip in a new product provided with an RAM having a size smaller than in the conventional product. In such a product as well, the I/O buffer or the protection circuit has been arranged proximate to the pad.
In summary, such measures as-reduction in size of a circuit element for reducing the chip size or arrangement of the CPU, the RAM and the ROM so as not to leave an empty space have conventionally been taken. Once the chip size is determined, however, it has not been easy to reduce the chip size in the case of change in the size of the RAM or the ROM.